One downside of wafer-to-wafer bonding is that it can produce a significant loss of real estate. In some photonic applications, for example, there is a low fill factor for the target wafer that is equipped with electro-optical elements. On the other hand, the wafer sizes in CMOS technology are generally not the same as those used in the compound semiconductor industry.
It is important to also note that there several key advantages with wafer-to-wafer bonding, such as collective pre-processing of the dies and high bonding throughput, which are strengths that are impossible to provide with die-to-die bonding.
Fortunately, it is possible to combine the best of both worlds by employing fast distribution of known good die, using high-quality direct bonding at the wafer level. This approach reduces the sensitivity to thermally induced stress and decouples the yields to the two processes, so long as known good die are only placed on known good sites on the wafer. Tuning the bonding conditions is relatively easy, because collective bonding is possible at elevated temperatures, even in vacuum conditions.
For a wafer-level die transfer process to be successful, it is essential to apply an appropriate, uniform pressure to every single die. This is not easy, due to factors such as bow and warp of wafers, uneven substrates and differences in die height. Introducing a compliant layer addresses all these challenges by enabling the application of similar force on different die, thus providing optimal transfer rates and high bonding yield.
Thanks to this process, heterogeneous integration can be scaled up to larger substrates and multiple functions can be added to the device wafer, even in volume production. This process – and that involving wafer-to-wafer bonding – will help to drive a new era for innovative device structures with novel functionalities and increased performance.
Click to read the in-depth article "Enabling silicon photonics
through advances in III-V integration on silicon" by EVG published in Semiconductor Today.
Advanced chip-to-wafer bonded dies on a 200mm wafer